1. Field of the Invention
The present invention relates to a method of forming a device isolation region, and more particularly to a method of forming a device isolation region by burying a dielectric film in a trench groove.
2. Description of the Related Art
As a structure for achieving electric isolation between devices formed on a semiconductor substrate, there is known a device isolation structure (hereafter referred to as "trench device isolation structure") formed by burying a dielectric film in a trench groove. Such a trench device isolation structure is formed, for example, as shown in FIGS. 2(a) to 2(e).
First, a thermal oxide film 22 made of siliconoxide is formed on a surface of a semiconductor substrate 21. Then, a silicon nitride film 23 is deposited on the thermal oxide film 22 by the chemical vapor deposition (CVD) method (FIG. 2(a)).
A mask is then formed by the photolithography technique, and this mask is used to process the silicon nitride film 23, the thermal oxide film 22 and the semiconductor substrate 21 by anisotropic etching, so as to form a trench groove. Here, a silicon portion on the surface of the trench groove exposed by anisotropic etching has been damaged at an interface to an active region (i.e. the side surface of the trench groove), so that it is not preferable in quality. Therefore, a surface oxide film 24 is formed on the surface of the trench groove to keep good quality (FIG. 2(b)).
Subsequently, a silicon oxide layer 25 is buried in the trench groove by the CVD method utilizing an ozone-TEOS reaction or a high density plasma (FIG. 2 (c)). Then, after densifying the buried silicon oxide layer 25 (for example, in order allow the dielectric film made by the ozone-TEOS reaction to have a film quality similar to the thermal oxide film, it is necessary to carry out a thermal treatment at 1000 to 1100.degree. C. under a nitrogen atmosphere), the surface of the substrate is planarized, for example, by the CMP method (FIG. 2(d)).
Here, if the film quality varies, the bad quality portion will show a large etching rate in a wet etching step carried out several times later. This leads to generation of a concavity at that portion. In order to prevent this concavity generation, the buried silicon oxide layer 25 is densified so that the etching rate of the silicon oxide layer 25 will be approximately equal to that of a thermal oxide film having a good quality.
Further, the silicon oxide film 25 (the silicon oxide film other than the one in the trench groove) and the silicon nitride film 23 on the surface are removed to complete a trench device isolation structure in which the silicon oxide layer is buried in the trench groove (FIG. 2(e)).
However, by burying the silicon oxide layer in the trench groove and conducting a thermal treatment to density the silicon oxide layer, a stress is generated in the semiconductor substrate due to contraction caused by the densification of the buried silicon oxide layer. As a result of this, crystal defects such as sliding and dislocation are generated in crystal lattices in the semiconductor substrate by a thermal treatment step such as thermal oxidation or thermal diffusion of injected impurity ions or the like after the trench groove is formed. This raises a problem that a leak current is generated through the crystal defects to decrease the device isolation efficiency.